CONTROL OF ENERGY EFFICIENCY IN INDUSTRY AND HOUSING AND COMMUNAL SERVICES
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UDC 004.72
The Analysis of Approaches for the Synthesis of Networks-on-chip by Using Regular Topologies
A.Yu. Romanov, Moscow Institute of Electronics and Mathematics, National Research University “Higher School of Economics”, Moscow, Russian Federation, a.romanov@hse.ru
Abstract
The article gives a review of existing methods of networks-on-chip design, based on the approach, in which the projection of the characteristic tasks graph is performed on a given regular topology. The general problem of the synthesis of networks-on-chip is characterized. The network topology can be foreknown (usually a regular topology) or selected in accordance with the tasks that will be performed by the network-on-chip. The first method of synthesis of networks-on-chip is widespread among the developers due to its relative simplicity and obviousness and presented in a variety of implementations, which are reviewed in this article. The advantages and disadvantages of this approach, the effect achieved by its application to various implementations of networks-on-chip and the way of its improvement, which is to extend the scope of solutions for regular network topologies on the predetermined irregular topologies with better characteristics are offered.
Keywords
network-on-chip, system-on-chip, network-on-chip regular topology, network-on-chip irregular topology, networks-on-chip design, networks-on-chip synthesis, problems characteristic graph
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Source
Bulletin of the South Ural State University. Ser. Computer Technologies, Automatic Control, Radio Electronics, 2015, vol. 15, no. 1, pp. 133-138. (in Russ.) (Brief Reports)