Sign | Register
UDC 004.72
The Analysis of Approaches for the Synthesis of Networks-on-chip by Using Regular Topologies
A.Yu. Romanov, Moscow Institute of Electronics and Mathematics, National Research University “Higher School of Economics”, Moscow, Russian Federation,
The article gives a review of existing methods of networks-on-chip design, based on the approach, in which the projection of the characteristic tasks graph is performed on a given regular topology. The general problem of the synthesis of networks-on-chip is characterized. The network topology can be foreknown (usually a regular topology) or selected in accordance with the tasks that will be performed by the network-on-chip. The first method of synthesis of networks-on-chip is widespread among the developers due to its relative simplicity and obviousness and presented in a variety of implementations, which are reviewed in this article. The advantages and disadvantages of this approach, the effect achieved by its application to various implementations of networks-on-chip and the way of its improvement, which is to extend the scope of solutions for regular network topologies on the predetermined irregular topologies with better characteristics are offered.
network-on-chip, system-on-chip, network-on-chip regular topology, network-on-chip irregular topology, networks-on-chip design, networks-on-chip synthesis, problems characteristic graph
1. Parallel Scalability of Video Decoders / C. Meenderinck, A. Azevedo, B. Juurlink, M.A. Messa, A. Ramires // Journal of Signal Processing Systems, 2009, vol. 57, no. 2, pp. 173–194.
2. Answer Set versus Integer Linear Programming for Automatic Synthesis of Multiprocessor Systems from Real-Time Parallel Programs / H. Ishebabi, P. Mahr, C. Bobda, M. Gebser, T. Shaub // International Journal of Reconfigurable Computing, 2009. DOI:
3. A Layout-aware Analysis of Networks-on-chip and Traditional Interconnects for MPSoCs / F. Angiolini, P. Meloni, S.M. Carta, L. Raffo, L. Benini // IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2007, vol. 26. no. 3, pp. 421–434.
4. Axel J., Hannu T. Networks on Chip. Dordrecht: Kluwer Academic Publishers, 2003. 303 p.
5. Benini L., Bertozzi D. Network-on-chip Architectures and Design Methods // IEE Proceedings Computers & Digital Techniques, 2005, vol. 152, no. 2, pp. 261 272.
6. Godson-T: An Efficient Many-core Architecture for Parallel Program Executions/ D. Fan, N. Yuan, J. Zhang, Y. Zhou, W. Lin, F.L. Song, X. Ye, H. Huang, L. Yu, G. Long, H. Zhang, L. Liu // Journal of Computer Science and Technology, 2009, vol. 24, no. 6, pp. 1061–1073.
7. Marculescu R., Ogras U. Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives // IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2009, vol. 28, no. 1, pp. 3–21.
8. Jingcao H., Marculescu R. Energy-aware Mapping for Tile-based NoC Architectures under Performance Constraints // Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2003), 2003, pp. 233–239.
9. Chou C., Marculescu R. Contention-aware Application Mapping for Network-on-Chip Communication Architectures // IEEE International Conference on Computer Design (ICCD 2008), 2008, pp. 164–169.
10. Hu J., Marculescu R. Energy- and Performance-Aware Mapping for Regular NoC Architectures // IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005, vol. 24, no. 4, pp. 551–562.
11. Murali S., De Micheli G. Bandwidth-constrained Mapping of Cores onto NoC Architectures // Proceedings of the Conference on Design, Automation and Test in Europe (DATE’04), Paris, 2004, vol. 2, pp. 16–20.
12. Bertozzi D., Benini L. Xpipes: A Network-on-chip Architecture for Gigascale Systems-on-chip // IEEE Circuits and Systems Magazine, 2004, vol. 4, no. 2, pp. 18–31.
13. Murali S., Benini L., De Micheli G. Mapping and Physical Planning of Networks-on-chip Architectures with Quality-of-service Guarantees // Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC 2005), 2005, vol. 1, pp. 27–32.
14. Murali S., De Micheli G. SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs // 41st Conference on Design Automation (DAC’04), 2004, pp. 914–919.
15. Murali S. Methodologies for Reliable and Efficient Design of Networks on chips: Ph.D. dissertation / Stanford University, 2007. 272 p.
16. Srinivasan K., Chatha K.S. A technique for Low Energy Mapping and Routing in Network-on-chip Architectures // Proceedings of the 2005 International Symposium on Low Power Electronics and Design (ISLPED’05), 2005, pp. 387–392.
17. Rhee C., Jeong H.Y., Ha S. Many-to-many Core-switch Mapping in 2-D Mesh NoC Architectures // IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004 (ICCD 2004). Proceedings. 2004. pp. 438–443.
18. Hansson A., Goossens K., Radulescu A. A Unified Approach to Mapping and Routing on a Network-on-chip for Both Best-effort and Guaranteed Service Traffic // VLSI Design, 2007, pp. 1–16.
19. Starobinski D., Karpovsky M., Zakrevski L.A. Application of Network Calculus to General Topologies Using Turn prohibition // IEEE/ACM Transactions on Networking (TON), 2003, vol. 11, no. 3, pp. 411–421.
20. Ascia G., Catania V., Palesi M. Multi-objective Mapping for Mesh-based NoC Architectures // Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/software Codesign and System Synthesis (CODES+ISSS’04), 2004, pp. 182–187.
21. Lei T., Kumar S. A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture // Euromicro Symposium on Digital System Design. Proceedings. 2003. pp. 180–187.
22. Thermal-aware IP Virtualization and Placement for Networks-on-chip Architecture / W. Hung, C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijakrishan, M.J. Irwin // IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004 (ICCD 2004). Proceedings. 2004. pp. 430–437.
23. Skadron K., Stan M.R., Huang W. Temperature-aware Microarchitecture // Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA’03), 2003, vol. 31, no. 2, pp. 2–13.
24. Whelihan D. The NOCsim Simulator Users Guide: Version 2.0. Pittsburgh: CMU, 2003. 51 p.
25. Addo-Quaye C. Thermal-aware Mapping and Placement for 3-D NoC Designs // IEEE International SOC Conference. Proceedings. 2005. pp. 25–28.
26. Hung W., Xie Y., Vijaykrishnan N. Thermal-aware Floorplanning Using Genetic Algorithms // Sixth International Symposium on Quality of Electronic Design (ISQED 2005), 2005, pp. 634–639.
27. Xie Y., Hung W. Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design // Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 2006, vol. 45, no. 3. pp. 177–189.
28. Shin D., Kim J. Power-aware Communication Optimization for Networks on chips with Voltage Scalable Links // International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004), 2004, pp. 170–175.
29. Schmitz M.T., Al-Hashimi B.M. Considering Power Variations of DVS Processing Elements for Energy Minimization in Distributed Systems // Proceedings of the 14th International Symposium on Systems Synthesis (ISSS’01), 2001, pp. 250–255.
Bulletin of the South Ural State University. Ser. Computer Technologies, Automatic Control, Radio Electronics, 2015, vol. 15, no. 1, pp. 133-138. (in Russ.) (Brief Reports)